Anti-Tamper Digital Clocks - An Overview
Anti-Tamper Digital Clocks - An Overview
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Consequently, the existing invention is not intended to be limited to the embodiments revealed herein but would be to be accorded the widest scope in keeping with the ideas and novel attributes disclosed herein.
In other additional thorough components of the invention, Every from the plurality of delayed monotone signals comprises possibly a a single or possibly a zero. The Assess circuit may perhaps establish regardless of whether the number of ones in the plurality of delayed monotone signals differs from a water stage quantity by more than a predetermined threshold.
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four. The method for detecting clock tampering as defined in declare 1, wherein the Assess circuit decides regardless of whether the number of ones while in the plurality of delayed monotone indicators differs from a h2o level range by much more than a predetermined threshold.
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twelve. The equipment for detecting clock tampering as defined in declare 11, wherein the h2o amount amount is set according to delayed monotone alerts from one or more former clock Assess time.
The reset time frame could be just before the Assess time period 310. Utilizing the clock CLK to trigger the Examine circuit 220 may perhaps utilize a clock edge at an stop from the Examine period of time to set off the Examine circuit.
31. The equipment for detecting voltage tampering as described in declare 30, more comprising: implies for resetting the indicates for delaying the monotone sign through a reset time frame, wherein the reset time period is previous to the Assess period of time.
The get more info current invention relates normally to detecting tampering Using the clock and/or source voltage of the processor.